1. Field of the Invention
The present invention relates to a semiconductor processing technology; and more particularly, to an ion implanter to improve uniformity of transistor parameters and an implantation method using the same.
2. Description of Related Arts
Generally, a transistor formation method includes several steps. First, a gate structure is formed on a substrate, and a gate spacer is formed on both sidewalls of the structure. Afterward, an ion-implantation process for adjusting a threshold voltage is applied to predetermined regions of the substrate disposed beneath the gate structure and the spacer and then, another ion-implantation process for forming sources/drains is applied thereto.
However, in this transistor formation method the transistors are not uniformly formed on the entire regions of a wafer. For instance, a mask process and an etching process are required to form the gate spacers, and during the gate spacer formation, it is difficult to obtain uniform lengths of the gate spacers. It is also difficult to obtain uniformity in the gate structures with the stacked layers for each application of a gate structure process. Furthermore, during the ion-implantation processes, nonuniformity is exhibited in between the center of the wafer and edges of the wafer.
FIG. 1 is a diagram of a conventional ion implanter. As shown, the ion implanter includes a quadrupole magnet assembly 11, an X-scanner 12, a beam parallelizer 13, an accelerator 14 and a wafer 15. Quadrupole magnet assembly 11 assists in diverging and converging an ion beam transmitted from an ion beam source and includes quadrupole magnets for generating magnetic fields at an interspatial pole created between the quadrupole magnets. Further, quadrupole magnet assembly 11 is configured with a first magnet subassembly 11A and a second magnet subassembly 11B each with two South (S) poles and two North (N) poles.
X-scanner 12 deflects the ion beam passed through the quadrupole magnet assembly 11 to an X-axis, thereby aiding the ion beam to be uniformly implanted in a direction of the X-axis. The ion beam passed through X-scanner 12 is scanned to the X-axis direction. Next, the ion beam passes through beam parallelizer 13, implanting the ion beam in parallel in order to give directionality with respect to wafer 15. Afterward, the ion beam passes through accelerator 14. Herein, accelerator 14 provides the ion beam with a high level of energy sufficient to reach wafer 15. When the ion implantation process is carried out in a uniform manner using the above-described ion implanter, a transistor parameter is scattered as shown in FIG. 2.
FIG. 2 is a scatter diagram showing a scattering of transistor parameters in the center and edges of a wafer when a conventional ion implanter is used. At this time, the scatter diagram is obtained by analyzing doses of implanted ions in the wafer based on a thermal wave measurement method that measures degrees of deterioration in lattice structures.
As shown, the dose of implanted ions is higher at the edges than in the center; accordingly, the dose of implanted ions is not uniform on the wafer. For instance, the measured thermal wave value employed for inferring the dose of implanted ions in the center of the wafer is in a range from 939 to 944, whereas that in the edges of the wafer is in a range from 944 to 949.
This nonuniform scattering results from a threshold voltage of a transistor and other electric parameters differently set between the transistors because of various factors impeding uniformity of the wafer. For instance, the threshold voltage of the transistor at the center of the wafer is low, while the threshold voltage of the transistor at the edges of the wafer is high. This nonuniformity problem is expected to be severe in a wafer of 200 mm and even in a wafer of 300 mm.
To solve this nonuniformity problem, conventional technology has attempted to eliminate the discrepancy in uniformity between the center and the edges of the wafer by controlling the ion implantation recipe. For instance, when the center of the wafer and the edges of the wafer have a low transistor threshold voltage and a high transistor threshold voltage, respectively, the center region of the wafer is implanted with an increased dose while the edge region of the wafer is implanted with a decreased dose.
However, this approach of ion implantation causes a much higher transistor threshold voltage at the edges of the wafer because it is difficult to implant ion impurities with different required concentrations throughout the single wafer. That is, although it is possible to adjust the transistor parameters by controlling the ion implantation recipe, it is difficult to improve transistor characteristics at the desired region. Therefore, it is necessary to develop an ion implantation method that adjusts the transistor parameters to uniformly correspond to different uniformity states throughout the wafer.